Typically, a semiconductor memory cell array includes a plurality of memory cells MC arranged in rows and columns and has a plurality of word lines WL.sub.1, WL.sub.2, . . . , and WL.sub.n which intersect bit line pairs BL.sub.1, BL.sub.1 , BL.sub.2, BL.sub.2 , . . . , and BL.sub.m, BL.sub.m . A conventional arrangement is depicted in FIG. 1. Memory cells are located at intersections of word lines WL and bit lines of a plurality of bit line pairs. Each memory cell includes a capacitor for storing data and a MOS transistor for switching. A sense amplifier section 2 including a plurality of sense amplifiers is responsive to a column selection signal CSL and transfers data between selected memory cells and a data line pair DL, DL.
An address buffer (not shown) receives external address signals which are decoded by a row decoder 4 and a column decoder 6. The row decoder 4 supplies a word line selecting signal RSL to a word line driver 8 which drives a word line selected in accordance with the address signals. A column decoder 6 supplies the column selecting signal CSL to the sense amplifier section 2 to effect data transfer between the data lines DL, DL and the column selected in accordance with the addressed signals.
FIG. 2 is a detailed depiction of a portion of the arrangement shown in FIG. 1. Referring to FIG. 2, a word line WL.sub.i is connected to a gate of a MOS switching transistor Qs in a memory cell MC1. When the transistor Qs of memory cell MC1 is switched on by a signal on word line WLi, a data signal is transferred between the capacitor Cs of the memory cell MC1 and a bit line BL.sub.j connected to the memory cell MC1. In a reading operation, for example, the bit lines BL.sub.3 and BL.sub.3 of the illustrated bit line pair are precharged to a precharge voltage 1/2 Vdd (1/2 Vdd sensing). Similarly, a word line WL.sub.j is connected to a gate of a MOS switching transistor Qs of in a memory cell MC2. When the transistor Qs of memory cell MC2 is switched on by a signal on word line WL.sub.j, a data signal is transferred between the capacitor Cs of the memory cell MC2 and a bit line BL.sub.j connected to the memory cell MC2. When data stored in one of the memory cells is read onto one of the bit lines, a potential difference is generated between the bit lines BL.sub.j and BL.sub.j of the bit line pair. A bit line sense amplifier SA connected to the bit line pair BL.sub.j and BL.sub.j senses and amplifies this potential difference. As shown in FIG. 2, sense amplifier SA includes a CMOS flip-flop connected between the bit lines BL.sub.j and BL.sub.j . The CMOS flip-flop which includes transistors Q1, Q2, Q3, and Q4 is connected via a PMOS transistor Q11 and an NMOS transistor Q12 to a power source Vdd and ground Vss, respectively. The gates of transistors Q11 and Q12 receive trigger signals S.sub.0 and S.sub.0, respectively. A pair of NMOS transistors Q5 and Q6, connected between the bit lines BL.sub.j, BL.sub.j and the data lines DL, DL.sub.j form an input/output (I/O) gate. Responsive to a signal CSL.sub.j supplied from column decoder 6 (FIG. 1) to the I/O gate transistors Q5 and Q6, data signals are transferred between the bit lines BL.sub.j, BL.sub.j and the data lines DL, DL when the column j has been selected.
As the capacity of semiconductor memory devices has increased, the possibility that the devices will contain one or more defective memory cells has also increased. This problem adversely affects the yield of semiconductor memory device manufacturing processes. One technique for dealing with this problem is to utilize redundant memory cells which are provided in a semiconductor memory device to replace memory cells which are determined to be defective during device testing. Accordingly, a word line or a bit line to which a defective memory cell is connected may be replaced by a redundant word line or redundant bit line connected to redundant memory cells. An address of a defective memory cell may be programmed by blowing appropriate ones of the fuses in a redundancy control circuit. A redundant memory cell is selected when an address corresponding to a defective memory cell is input.
FIG. 3 illustrates a portion of a conventional dynamic random access memory with row redundancy. The memory portion includes memory cells MC1, MC2 and a redundant memory cell RMC1. The memory cells MC1 and MC2 are formed by a respective data storage capacitors Cs and transfer transistors Qs. Redundant memory cell RMC1 is formed by a data storage capacitor Cr and a transfer transistor Qr. The gates of the transfer transistors Qs, Qs of memory cells MC1, MC2 are connected to word lines WL.sub.i and WL.sub.j, respectively. The gate of the transfer transistor Qr of redundant memory cell RMC1 is connected to a redundant word line RDWL.sub.i. External address signals are supplied via an address buffer (not shown) to a row decoder which generates word line selecting signals RSLi, RSLj, . . . , etc. The word line selecting signals are supplied to word line driver WDR. The address buffer also forwards address signals to redundancy control circuit RRDN. RRDN generates word line drive signal WD and redundant word line drive signals RDWD1, RDWD2, . . . , RDWDj. WD is active when a memory cell on a normal word line is to be accessed. One of the redundant word line drive signals is active when a redundant memory cell on a redundant word line is to be accessed. The signals WD and RDWD1, RDWD2, . . . , RDWDj are forwarded to word line driver WDR and redundant word line driver RWDR, respectively. For each word line, WDR includes an AND gate. At each AND gate WD is ANDed with the respective word line selecting signal. When the word line WL.sub.i is driven by word line driver WDR, data may be read out or written to the data storage capacitor Cs of memory cell MC1 via bit line BLj. Similarly, when the word line WL.sub.j is driven by the word line driver WDR, data may be read out or written to the data storage capacitor Cs of the memory cell MC2 via the bit line BL.sub.j . The redundant memory cell RMC1 may replace either memory cell MC1 or MC2 if it is determined that one of these cells is defective. However, it can be seen that if the redundant memory cell RMC1 replaces the memory cell MC2, the physical data stored in capacitor Cr of redundant memory cell RMC1 for representing a given logical data bit will be inverted with respect to the physical data stored in capacitor Cs of memory cell MC2 for representing the same given logical data bit. In general, in semiconductor memory cell devices such as DRAMs, two logic states correspond to the arrangement and composition of the memory cell array. Half the memory cell array equals the true state of data to be read or written while the other half corresponds to the complementary state.
When a defective memory cell is detected and replaced by a redundant memory cell, the physical data state (i.e., bit pattern) in which a given bit is stored in a substituted redundant memory cell may differ (i.e., be inverted) from the physical data state in which that given bit is stored in the replaced memory cell. To avoid the possibility of a redundant memory cell storing bit information in a physical data state different from the physical data state in which the bit information is stored in the replaced memory cell, redundant memory cells can be substituted in a manner which ensures that the physical data states of the bit information stored in the redundant memory cells and the physical data state of bit information stored in the defective memory cells match. However, the efficiency of the redundancy cell is reduced with such an arrangement.
In light of the above, there is a need to increase redundancy efficiency with a small design space. A single redundancy word line replacement scheme for each defective word line employs a minimum number of elements. One such word line redundancy architecture is depicted in FIG. 4a. Shown in FIG. 4a are a word line driver 20, a memory cell array including a word line WL.sub.i, a redundant memory cell array including a redundant word line RDWL.sub.j, and a sense amplifier 30. According to this scheme, a redundant word line such as RDWL.sub.j may be substituted for a defective word line WL.sub.i. When RDWL.sub.j replaces WL.sub.i, the bit information will be inverted because the physical data states of the memory cells respectively coupled to word lines WL.sub.i and RDWL.sub.j are complementary. As a result, this architecture fails to maintain the original physical bit information. Consequently, during testing of the semiconductor memory device, both logical one and logical zero data must be supplied to the memory device in order, for example, to write physical one data to all the memory cells including the redundant memory cells. Likewise, both logical one and logical zero data must be supplied to the memory device in order to write physical zero data to all the memory cells including the redundant memory cells. The testing time for such a scheme is therefore long.
According to another conventional word line redundancy architecture depicted in FIG. 4b having like elements to FIG. 4a, four word lines are simultaneously replaced as a unit and accordingly the physical states of the original bit information is maintained. However, several drawbacks are associated with this structure. For example, the efficiency of the scheme is reduced to 1/4 the efficiency of the FIG. 4a scheme using the same number of redundant word lines. To match the efficiency of FIG. 4a, the scheme would require four times the number of redundant word lines. This arrangement may be suitable for low density DRAMs, but as density increases, the number of redundant word lines and disadvantages also increase.
According to the FIG. 4b redundancy architecture, the design space of the original bit increases in excess of 3% (6%) assuming an efficiency of four replaceable cells per 1 mega-bit (512 kilobits) sub-array used for a 256 mega-bit DRAM design. Higher efficiency would be expected for the 1 giga-bit DRAM or larger since the number of sub-arrays would be significantly greater increasing the probability of defective chips. The design space is thereby increased by more than 6% (12%) with an efficiency of 8 replaceable cells per 1 mega-bit (8 per 512 kilo-bits) of memory.
Consequently, there is a need to provide a redundancy architecture for high density semiconductor devices.